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W83194BR-SD W83194BG-SD Winbond Clock Generator For INTEL P4 Springdale Series Chipset
Date:
Mar./22/2006
Revision:
1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
W83194BR-SD/W83194BG-SD Revision history
VERSION DATE PAGE DESCRIPTION
n.a. 0.5 0.6 1.0 1.1 1.2 07/07/03 12/18/03 05/05/04 4/13/2005 12/20/2005 23 n.a. 7~15, 20
All of the versions before 0.50 are for internal use. First published preliminary version. Correction IC version, add register default value and correction some description and default value Update on web Add disclaimer Add Lead-free part number
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 5.3 5.4 5.5 5.6 6. 7. Crystal I/O ....................................................................................................................... 3 CPU, SRC, 3V66, PCI Clock Outputs ............................................................................ 3 Fixed Frequency Outputs ............................................................................................... 4 I2C Control Interface....................................................................................................... 4 Output Control Pins ........................................................................................................ 5 Power an GND Pins........................................................................................................ 5
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6 I2C CONTROL AND STATUS REGISTERS............................................................................... 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 Register 0: Frequency Select (Default =10H)................................................................. 7 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default = E3H) ........................ 7 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default = FFH) .................................. 8 Register 3: PCI, 3V66 Clock (1 = Enable, 0 = Disable) (Default = EFH)........................ 8 Register 4: 24_48 MHz, REF Control (1 = Enable, 0 = Disable) (Default =FCH)........... 8 Register 5: Watchdog Control (Default = 00H) ............................................................... 9 Register 6: Watchdog Timer (Default =08H) ................................................................ 10 Register 7: Asynchronous Program (Default = 40H) .................................................... 10 Register 8: M/N Program (Default = 8AH) .................................................................... 10 Register 9: M/N Program (Default = CEH) ................................................................... 11 Register 10: M/N Program (Default = 13H) .................................................................. 11 Register 11: Spread Spectrum Programming (Default = 2FH)..................................... 11 Register 12: Divider Ratio (Default = C6H)................................................................... 12 Register 13: Control (Default = 0FH) ............................................................................ 12 Register 14: Control (Default = 27H) ............................................................................ 13 Register 15: Control (Default =3CH)............................................................................. 13 Register 16: Control (Default = 24H) ............................................................................ 13 Register 17: Slew Rate Control (Default = 00H)........................................................... 14 Register 18: Slew Rate Control (Default = 00H)........................................................... 14 Register 19: Control (Default = 0AH)............................................................................ 15 Register 20: Winbond Chip ID - Project Code (Ready Only) (Default = 47H) ............. 15 - II -
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.22 8. 8.1 8.2 8.3 8.4 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10. 11. 12. Register 21: Reserved (Ready Only) (Default = 50H) .................................................. 16 Block Write Protocol ..................................................................................................... 17 Block Read Protocol ..................................................................................................... 17 Byte Write Protocol ....................................................................................................... 17 Byte Read Protocol....................................................................................................... 17 Absolute Maximum Ratings .......................................................................................... 18 General Operating Characteristics ............................................................................... 18 Skew Group Timing Clock ............................................................................................ 18 CPU 0.7V Electrical Characteristics ............................................................................. 19 SRC 0.7V Electrical Characteristics ............................................................................. 19 3V66 Electrical Characteristics ..................................................................................... 19 PCI Electrical Characteristics ....................................................................................... 20 24M, 48M Electrical Characteristics ............................................................................. 20 REF Electrical Characteristics ...................................................................................... 20 ACCESS INTERFACE .............................................................................................................. 17
SPECIFICATIONS .................................................................................................................... 18
ORDERING INFORMATION..................................................................................................... 21 HOW TO READ THE TOP MARKING...................................................................................... 21 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22
- III -
Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 1. GENERAL DESCRIPTION
The W83194BR-SD is a Clock Synthesizer for Intel P4 Springdale series chipset. W83194BR-SD provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, SRC, PCI, and 3V66 clocks setting. All clocks are externally selectable with smooth transitions. The W83194BR-SD provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides +/-0.25%, +/-0.5% center type and -0.5%, -1.0% down type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-SD also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-SD accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. FEATURES
* 2 pairs current mode differential clock for CPU and Chipset * 1 pairs current mode differential clock for SRC * 3 3V66 clock outputs * 1 3V66/VCH clock output default 66MHz * 9 PCI synchronous clocks, 3 free running * 2 48MHz clock outputs for USB and DOT * 1 24_48MHz for I/O chip, default 48MHz * 3 REF 14.318MHz clock outputs * SRC/AGP/PCI clock out supports synchronous and asynchronous mode * 3V66 leads PCICLK from 1.5ns to 3.5ns * I2C 2-Wire serial interface supports block and byte mode read/write * Step-less frequency programming * Smooth frequency switch with selections from 100 to 400MHz * Programmable clock outputs Slew rate control and Skew control * +/- 0.25% center type spread spectrum in table mode * Programmable S.S.T. scale to reduce EMI * Programmable registers to enable/stop each output and select modes * Watch Dog Timer and RESET# output pins * 48-pin SSOP package
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 3. PIN CONFIGURATION
FS1*/REF0 FS0*/REF1 REF2 VD DRE F XIN XOU T GN D FS2 & /PC ICLK_F0 FS4 & /PC ICLK_F1 PC ICLK_F2 VD DPCI GN D PCICLK 0 PCICLK 1 PCICLK 2 PCICLK 3 VD DPCI GN D PCICLK 4 PCICLK 5 SEL24_48# & /24_48M Hz & /48M Hz_USB FS3 48M Hz_DO T GN D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V DDA G ND IR EF RE SET# G ND CPUCLKT1 CPUCLKC1 V DDC PU CPUCLKT0 CPUCLKC0 G ND SR CCLKT SR CCLKC V DD V TT_PW RG D/PD#* SD ATA * SC LK* 3V 66_0 3V 66_1 G ND V DD3V 66 3V 66_2 3V 66_3/V CH/VCH _EN & V DD48
#: Active low *: Internal pull up resistor 120K to VDD
&
: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
D iv id e r
3
PLL2
48M H z_U SB , 48M H z_D O T , 24_48M H z
X IN XOUT
XTAL OSC
3
R E F 0 :2
PLL1 S p read S p e c tru m
V COCLK
2 2
C P U C L K _ T 0 :1 C P U C L K _ C 0 :1 SRCCLKT SRCCLKC
M /N /R a tio ROM D iv id e r
3
3 V 6 6 _ 3 /V C H 3 V 6 6 _ 0 :2
V TT_PW RG D F S < 0 :4 > V CH _EN &
L a tc h & POR
9
P C IC L K _ 0 :5 , P C IC L K _ F 0 :2
PD#& SEL24_48#&
C o n tro l L o g ic & C o n fig R e g is te r
RESET#
R ref SDATA* SCLK* I2 C In te rfa c e
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtd120k INtp120k OUT OD I/O I/OD # *
&
Input Latch input pin and internal 120K pull down Latch input pin and internal 120K pull up Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain Active Low Internal 120k pull-up Internal 120k pull-down
5.1
Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
5 6
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318 MHz nominally with internal loading capacitors (18pF).
5.2
CPU, SRC, 3V66, PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
40, 43, 39, 42 37, 36 26 31, 30, 27
CPUCLKT [0:1] CPUCLKC [0:1] SRCCLKT, SRCCLKC 3V66_3/VCH VCH_EN
&
OUT OUT OUT INtd120k OUT OUT INtd120k
0.7V Current mode differential clock outputs for CPU and Chipset. 0.7V Current mode differential clock outputs for Chipset, 100 MHz(default) or 200 MHz outputs selected by I2C register. 66 MHz(default) or 48 MHz outputs selected by hardware trapping data on 26 pin VCH_EN& selecting. 3.3V output clocks for the chipset and AGP slot. PCI clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down.
3V66_0, 3V66_1, 3V66_2 PCICLK_F0
8
FS2&
-3-
Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
CPU, SRC, 3V66, PCI Clock Outputs continued
PIN
PIN NAME
TYPE
DESCRIPTION
PCICLK7_F1 9 FS4& PCICLK_F2 PCICLK [0:5]
OUT INtd120k OUT OUT
PCI clock output. Latched input for FS4 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. PCI clock outputs. PCI clock outputs.
10 13, 14, 15, 16, 19, 20
5.3
PIN
Fixed Frequency Outputs
PIN NAME TYPE DESCRIPTION
REF0 1 FS1* REF1 2 3 21 SEL24_48#& 22 48 MHz_USB FS3& 23 48 MHz_DOT FS0* REF2 24_48 MHz
OUT INtp120k OUT INtp120k OUT OUT INtd120k OUT INtd120k OUT
14.318 MHz output. Latched input for FS1 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull up. 14.318 MHz output. Latched input for FS0 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull up. 14.318 MHz output. 48 MHz clock output. Latched input at initial power up for 24_48 MHz selecting the output frequency clocks. This is internal 120K pull down, 1 = 24 MHz, 0 = 48 MHz (default). 48 MHz clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency clocks. This is internal 120K pull down. 48 MHz clock output.
5.4
PIN
I2C Control Interface
PIN NAME TYPE
2
DESCRIPTION
33 32
SDATA* SCLK*
I/OD IN
Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor.
-4-
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
5.5
PIN
Output Control Pins
PIN NAME TYPE DESCRIPTION
Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. The table is show as follows. 46 IREF IN
Board Target Trace 50 Ohms Reference R, Iref R = 475 Iref = 2.32mA Output Current Ioh = 6*Iref Ioh @ Z 0.7V @ 50
45
RESET# VTT_PWRGD
OD
System reset signal when the watchdog is time out. This pin will generate 250 mS when the watchdog timer is timeout. Power good input signal comes from ACPI with high active. This 3.3V input is level sensitive strobe used to determine FS [4:0] input are valid and is ready to sample. This pin is high active. Power Down Function. This is internal 120K pull up. This is multifunction pin. When the VTT_PWRGD signal is asserted (this is, turns from a logical Low to high), the pin will be switched into the function of power down (PD#).
IN
34 PD#* IN
5.6
Power an GND Pins
PIN PIN NAME TYPE DESCRIPTION
4 11, 17 25 28 35 41 48 7, 12, 18, 24, 29, 38, 44, 47
VDDREF VDDPCI VDD48 VDD3V66 VDD VDDCPU VDDA GND
PWR PWR PWR PWR PWR PWR PWR PWR
3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for 48 MHz. 3.3V power supply for 3V66. 3.3V power supply. 3.3V power supply for CPU. 3.3V power supply analog core. Ground pin for 3.3 V
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3).
FS4 FS3 FS2 FS1 FS0 CPU (MHZ) SRC (MHZ) 3V66(MHZ) PCI (MHZ)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
100.0 200.0 133.3 166.6 200.0 400.0 266.6 333.3 100.9 202 134.6 168.3 115 230 153.3 191.6 100 200 133.3 166.6 200 400 266.6 333.3 105 210 140 175 110 220 146.6 183.3
100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200 100/200
66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6 66.6
33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 7. I2C CONTROL AND STATUS REGISTERS
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1
BIT
Register 0: Frequency Select (Default =10H)
NAME PWD DESCRIPTION
7 6 5 4 3 2
SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL
0 0 0 1 0 Enable software table selection FS [4:0]. 0 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output. Software frequency table selection through I2C
1
SPSPEN
0
0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable After watchdog timeout
0
EN_SAFE_FRE Q
0
0 = Reload the hardware FS [4:0] latched pins setting. 1 = Reload the desirable frequency table selection defined at Reg-5 Bit 4~0.
7.2
BIT
Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default = E3H)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SRCCLKT SRCCLKC CPUCLKT1 CPUCLKC1 CPUCLKT0 CPUCLKC0 FS4 FS3 FS2 FS1 FS0
1 1 1 X X X X X
Pin 37,36 SRCCLK T/C output control Pin 43,42 CPUCLKT1/C1 output control Pin 40,39 CPUCLKT0/C0 output control Power on latched value of FS4 (9) pin, Default 0 (Read only) Power on latched value of FS3 (22) pin. Default 0 (Read only) Power on latched value of FS2 (8) pin. Default 0 (Read only) Power on latched value of FS1 (1) pin. Default 1 (Read only) Power on latched value of FS0 (2) pin. Default 1 (Read only)
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.3
BIT
Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default = FFH)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI_F2 PCI_F1 PCI_F0 Reserve PCI_5 PCI_4 Reserve PCI3
1 1 1 1 1 1 1 1
Pin 10 PCI_F2 output control Pin 9 PCI_F1 output control Pin 8 PCI_F0 output control Reserved Pin 20 PCI5 output control Pin 19 PCI4 output control Reserved Pin 16 PCI3 output control
7.4
BIT
Register 3: PCI, 3V66 Clock (1 = Enable, 0 = Disable) (Default = EFH)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI2 PCI1 PCI0 VCH_EN 3V66_3 3V66_2 3V66_1 3V66_0
1 1 1 X 1 1 1 1
Pin 15 PCI2 output control Pin 14 PCI1 output control Pin 13 PCI0 output control Pin 26 3V66_3 / VCH output select 1: VCH output, 0: 3V66 output (Default) Default value follow hardware trapping data on VCH_EN& pin 26. Pin 26 3V66_3 / VCH output control Pin 27 3V66_2 output control Pin 30 3V66_1 output control Pin 31 3V66_0 output control
7.5
BIT
Register 4: 24_48 MHz, REF Control (1 = Enable, 0 = Disable) (Default =FCH)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
24_48 MHz DOT48 USB48 REF2 REF1 REF0 MODE1 MODE0
1 1 1 1 1 1 0 0
Pin 21 24_48 MHz output control Pin 23 DOT48 output control Pin 22 USB48 output control Pin 3 REF2 output control Pin 2 REF1 output control Pin 1 REF0 output control Clock output mode selection Refer to Table-1
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
Table-1: Clock output mode selection
MODE NORMAL MODE 00 CPU OVER CLOCK MODE 01 CPU/SRC OVER CLOCK MODE 10
MODE1/0 CPU over clock SRC over clock AGP/PCI over clock Spreading
Byte 8 & 9 Byte 8 & 9 Byte 8 & 9 All clocks are Effective
Byte 8 & 9 Byte 4 & 10 (asynchronous) Byte 4 & 10 (asynchronous) CPU is effective Only.
Byte 8 & 9 Byte 8 & 9 Byte 4 & 10 (asynchronous) CPU and SRC are Effective.
7.6
BIT
Register 5: Watchdog Control (Default = 00H)
NAME PWD DESCRIPTION
7
SEL24
X
Pin 21 24 / 48 MHz output selection 1: 24 MHz, 0: 48 MHz. (Default) Default value follow hardware trapping data on SEL24_48# pin. Program this bit => 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0
6
EN_WD
0
5
WD_TIMEOUT
0
Read Back only. Timeout Flag. 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting.
4 3 2 1 0
SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 0 0 These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ = 1.
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.7
BIT
Register 6: Watchdog Timer (Default =08H)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0]
0 0 0 0 1 0 0 0 Setting the down count depth. One bit resolution represents 250 mS. Default time depth is 8*250 mS = 2.0 second. If the watchdog timer is counting, this register will return present down count value.
7.8
BIT
Register 7: Asynchronous Program (Default = 40H)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Tri-state Reserve Reserve Reserve Reserve Reserve ASEL<1> ASEL<0>
0 1 0 0 0 0 0 0
Tri-state all output if set 1 Reserved Reserved Reserved Reserved Reserved Asynchronous AGP/PCI frequency table selection ASEL<1:0> 00: 66.6 MHz 10: 79.9 MHz 01:72.1 MHz 11:68.7 MHz
7.9
BIT
Register 8: M/N Program (Default = 8AH)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [8] M_DIV [6] M_DIV [5] M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 0 0 0 1 0 1 0
Programmable N divisor value. Bit 7 ~0 are defined in the Register 8.
Programmable M divisor value.
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.10 Register 9: M/N Program (Default = CEH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
1 1 0 0 1 1 1 0 Programmable N divisor value bit 7 ~ 0. The bit 8 is defined in Register 7.
7.11 Register 10: M/N Program (Default = 13H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserve N3<6> N3<5> N3<4> N3<3> N3<2> N3<1> N3<0>
0 0 0 1 0 0 1 1
Reserved
Programmable N3 divisor bit 6 ~ 0 for synchronism SRC/AGP/PCI clock.
7.12 Register 11: Spread Spectrum Programming (Default = 2FH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 1 0 1 1 1 1
Spread Spectrum Up Counter bit 3 ~ bit 0.
Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000
- 11 -
Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.13 Register 12: Divider Ratio (Default = C6H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SRC_H DS9 DS5 DS4 DS3 DS2 DS1 DS0
1 1 0 0 0 1 1 0
SRC frequency select, 1: 100 MHz, 0: 200 MHz Define the AGP divider ratio, Table-2 integrate the all divider configuration Define the AGP divider ratio Table-2 integrate the all divider configuration Define the SRC divider ratio Refer to Table-2 Define the SRC divider ratio Refer to Table-2
Table-2 CPU, SRC, AGP, PCI divider ratio selection Table LSB MSB Bit1/ Bit3/Bit6 0 1 0 Div2 Div4 CPU Bit0 1 Div3 Div5 0 Div2 Div4 SRC Bit2 1 Div3 Div5 00 Div5 Div10 01 Div6 Div12 AGP Bit5, 4 10 Div7 Div12 11 Div8 Div12
7.14 Register 13: Control (Default = 0FH)
BIT NAME PWD DESCRIPTION
7
EN_MN_PROG
0
0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<4:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg9 - bit 7). Reserved Reserved
6 5 4 3 2 1 0
Reserve Reserve Reserve IVAL<3> IVAL<2> IVAL<1> IVAL<0>
0 0 0 1 1 1 1
Charge pump current selection
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.15 Register 14: Control (Default = 27H)
BIT NAME PWD DESCRIPTION
CPUT output state in during POWER DOWN or Stop mode assertion. 7 CPUT_DRI 0 1: Driven (2*Iref), 0: Tristate (Floating) CPUC always tri-state (floating) in power down Assertion. SRC_T output state in during POWER DOWN or Stop mode assertion. 6 5 4 3 2 1 0 SRCT_DRI SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0] 0 1 0 0 1 1 1 Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us 1: Driven (6*Iref), 0: Tristate (Floating) SRC_C always tri-state (floating) in power down Assertion.
7.16 Register 15: Control (Default =3CH)
BIT NAME PWD DESCRIPTION
7 6 5 4
INV_CPU Reserve Reserve SPSP1
0 0 1 1
Invert the CPU phase 0: Default, 1: Inverse Reserved Reserved Spread Spectrum type select. 00: Down 1% 01: Down 0.5% 10: Center 0.5% 11: Center 0.25%
3
SPSP0
1
2 1 0
ASKEW [2] ASKEW [1] ASKEW [0]
1 0 0 CPU to AGP skew control.
7.17 Register 16: Control (Default = 24H)
BIT NAME PWD DESCRIPTION
7 6
INV_AGP INV_PCI
0 0
Invert the AGP phase 0: Default, 1: Inverse Invert the PCI phase 0: Default, 1: Inverse
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
Register 16: Control (Default = 24H), continued
BIT
NAME
PWD
DESCRIPTION
5 4 3 2 1 0
SSKEW [2] SSKEW [1] SSKEW [0] PSKEW [2] PSKEW [1] PSKEW [0]
1 0 0 1 0 0 CPU to PCI skew control CPU to SRC skew control
7.18 Register 17: Slew Rate Control (Default = 00H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI_F2_S2 PCI_F2_S1 PCI_F0_S2 PCI_F0_S1 AGP_32_S2 AGP_32_S1 AGP_10_S2 AGP_10_S1
0 0 0 0 0 0 0 0
PCI_F2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI_F1 / PCI_F0 slew rate control 11: Strong, 00: Weak, 10/01: Normal 3V66_3 / 3V66_2 slew rate control 11: Strong, 00: Weak, 10/01: Normal 3V66_1 / 3V66_0 slew rate control 11: Strong, 00: Weak, 10/01: Normal
7.19 Register 18: Slew Rate Control (Default = 00H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI_75_S2 PCI_75_S1 PCI_42_S2 PCI_42_S1 PCI_10_S2 PCI_10_S1 REF_S2 REF_S1
0 0 0 0 0 0 0 0
PCI7, 6, 5 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI4, 3, 2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal REF slew rate control 11: Strong, 00: Weak, 10/01: Normal
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.20 Register 19: Control (Default = 0AH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPUSTOP_EN PCISTOP_EN SRCS_EN INV_DOT48 INV_USB48 USB48_S2 USB48_S1 INV_SRC
0 0 0 0 1 0 1 0
Stop all CPU clocks. 1: Enable stop feature, 0: Disable Stop SRC clock and all PCI clocks except free running parts. 1: Enable stop feature, 0: Disable Allow PCISTOP pin to affect SRC output state 1: Allow, 0: Ignore the PCISTOP pin effect (Free running) Invert the DOT48 phase 0: In phase with USB48, 1: 180 degrees out of phase Invert the USB48 phase 0: In phase with DOT48, 1: 180 degrees out of phase USB48/DOT48/USB24_48 slew rate control 11: Strong, 00: Weak, 10/01: Normal Invert the SRC phase, 0: Default, 1: Inverse
7.21 Register 20: Winbond Chip ID - Project Code (Ready Only) (Default = 47H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0 1 0 0 0 1 1 1
Winbond Chip ID. W83194BR-SD (SA5847). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.22 Register 21: Reserved (Ready Only) (Default = 50H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 1 0 1 0 0 0 0
Reserved Reserved
Reserved Reserved
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 8. ACCESS INTERFACE
The W83194BR-SD provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-SD is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2.
Block Read and Block Write Protocol
8.1 Block Write Protocol
8.2
Block Read Protocol
## In block mode, the command code must filled 00H
8.3
Byte Write Protocol
8.4
Byte Read Protocol
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 9. SPECIFICATIONS
9.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection (Human body model)
-0.5V to +4.6V -0.5 V to +4.6 V 3.135V to 3.465V 3.135V to 3.465V -65C to +150C -55C to +125C 0C to +70C 2000V
9.2
General Operating Characteristics
PARAMETER SYM. MIN. MAX. UNITS TEST CONDITIONS
VDDREF = VDDA = VDDCPU = VDD3V66 = VDDPCI = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10pF
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
VIL VIH VOL VOH Idd Cin Cout Lin
0.8 2.0 0.4 2.4 350 5 6 7
VDC VDC VDC VDC mA pF pF nH
All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 400 MHz PCI = 33.3 MHz with load
9.3
Skew Group Timing Clock
PARAMETER MIN. TYP. MAX. UNITS TEST CONDITIONS
VDDREF = VDDA = VDDCPU = VDD3V66 = VDDPCI = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10 pF
3V66 to PCI Skew CPU to CPU Skew 3V66 to 3V66 Skew PCI to PCI Skew 48 MHz to 48 MHz Skew REF to REF Skew
1.5
2.6
3.5 100 250 500 1000 500 - 18 -
nS pS pS pS pS pS
Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
9.4 CPU 0.7V Electrical Characteristics
VDDA = VDDCPU= 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.14V, Voh = 0.56V, Vr = 475, IREF = 2.32 mA, Ioh = 6*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute Crossing Point Voltages Cycle to Cycle Jitter Duty Cycle
175 175 250 45
700 700 550 125 55
pS pS mV pS %
100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz
9.5
SRC 0.7V Electrical Characteristics
VDD = 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.14V, Voh = 0.56V, Vr = 475, IREF = 2.32 mA, Ioh = 6*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle
175 175 250 45
700 700 550 125 55
pS pS mV pS %
100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz
9.6
3V66 Electrical Characteristics
PARAMETER MIN. MAX. UNITS TEST CONDITIONS
VDD3V66 = 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
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Publication Release Date: March, 22, 2006 Revision 1.2
W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
9.7 PCI Electrical Characteristics
PARAMETER MIN. MAX. UNITS TEST CONDITIONS
VDDPCI= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF,
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
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9.8
24M, 48M Electrical Characteristics
PARAMETER MIN. MAX. UNITS TEST CONDITIONS
VDD48 = 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF,
Rise Time Fall Time Long Term Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 500 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
9.9
REF Electrical Characteristics
PARAMETER MIN. MAX. UNITS TEST CONDITIONS
VDDREF= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10 pF
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
1000 1000 45 -33
4000 4000 1000 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
30 38
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83194BR-SD W83194BG-SD
48 PIN SSOP 48 PIN SSOP (Pb-free package)
Commercial, 0C to +70C Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83194BR-SD 28051234 340GBBSA W83194BG-SD 28051234 340GBBSA
1st line: Winbond logo and the type number: W83194BR-SD, W83194BG-SD 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 340 G B B SA 340: packages made in '2003, week 40 G: assembly house ID; L means Lingsen, O means OSE, G means GR B: Internal use code B: IC revision SA: mask version All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Publication Release Date: March, 22, 2006 Revision 1.2
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W83194BR-SD/W83194BG-SD
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 12. PACKAGE DRAWING AND DIMENSIONS
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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